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Showing posts from January, 2023

The Verification story

     They were the B. Tech days, and we were taught about Verilog and VHDL programming languages. Obviously, learning the syntax was never enough. We need to use it - have to write programs.      As it is a hardware language, we need to develop the codes for electronic blocks. Starting with trivial ones like AND gates, and OR gates and going up to priority encoder, kind of blocks.     However, we are taught that that was not enough. We need to code another part, which is called "testbench."  We were given a few examples of the test benches for some blocks. Honestly, the testbench part looked almost the same for all the designs. We simply concluded that the test bench was easier to code than the design part.     Cut to the training period in the initial days of the core company. The good news is that the hardware languages we were taught and that the companies use are almost similar, even though that is not enough. After the basic training, there is the assignment of domains t